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the HM63021 is a 2048-word 8-bit static serial access memory (sam) with separate data inputs and outputs. since it has an internal address count- er, no external address signal is required and inter- nal addresses are scanned serially. using five dif- ferent address scan modes, it is applicable to fifo memories, double-speed conversions, 1h delay lines, and 1h/2h delay lines for digital tv signals. its minimum cycle times are 28 ns and 34 ns, cor- responding to 8 fsc of pal tv and ntsc tv sig- nals. all inputs and outputs are ttl-compatible. features five modes for various applications corresponds to digital tv system with 4 fsc sampling (pal, ntsc) decoder signal output pin (fewer external circuits) asynchronous read/write operation separate address counters for read/write no address input required high speed (cycle time 28/34/45 ns (min)) completely static memory (no refresh required) 8-bit sam with separate i/o low power (250 mw typ active) single 5 v supply ttl compatible ordering information cycle type no. time package HM63021p-28 28 ns HM63021p-34 34 ns HM63021p-45 45 ns HM63021p28n 28 ns HM63021fp-28 28 ns HM63021fp-34 34 ns HM63021fp-45 45 ns HM63021fp28n 28 ns 28-pin plastic sop (fp-28da) 300-mil, 28-pin plastic dip (dp-28n) 1 HM63021 series 2048-word 8-bit line memory pin arrangement 1 mode1 v cc 28 2 rclk mode2 27 3 rres mode3 26 4 din0 oe 25 5 din1 dout0 24 6 din2 dout1 23 7 din3 dout2 22 8 din4 dout3 21 9 din5 dout4 20 10 din6 dout5 19 11 din7 dout6 18 12 we dout7 17 13 high z wres 16 14 v ss wclk 15 modes d 1h/2h tbc dsc tbce tbce dsc tbc 1h/2h d rdec dec2 dec3 dec4 ds wt dec1 wdec clk res read control input output write control (top view)
pin description pin no. pin name functions 1 mode1 mode input 1 (all modes) 2 rclk / clk read clock input (tbce, dsc, tbc) clock input (1h/2h, d) 3 rres / res read reset input (tbce, dsc, tbc) reset input (1h/2h, d) 4 to 11 din 0 to din 7 data inputs (all modes) 12 we write enable input (all modes) 13 high-z/ wdec / dec1 high impedance (tbce, dsc) write decode pulse output (tbc) decode pulse output 1 (1h/2h, d) 14 v ss ground (all modes) 15 wclk / wt / dec4 write clock input (tbce, dsc, tbc) write timing input (1h/2h) decode pulse output 4 (d) 16 wres /ds/ dec3 write reset input (tbce, dsc, tbc) delay select input (1h/2h) decode pulse output 3 (d) 17 to 24 dout 0 to dout 7 data outputs (all modes) 25 oe output enable input (all modes) 26 mode3/ rdec / dec2 mode input 3 (tbce) read decode pulse output (tbc) decode pulse output 2 (1h/2h, d) 27 mode2 mode input 2 (all modes) 28 v cc power supply (+5 v) (all modes) mode table mode signals mode1 mode2 mode3 mode application example h h h time base compression/expansion (tbce) picture in picture h h l double speed conversion (dsc) non interlace hl *1 time base correction (tbc) time base corrector lh *1 1h/2h delay (1h/2h) vertical filter ll *1 delay line (d) delay line note: 1. decoder output signal ( rdec , dec2 ) 2 HM63021 series HM63021 series
3 HM63021 series HM63021 series block diagram we din0 din7 v cc v ss input latch we latch write address control address decoder write column decoder write column switch write stop write row decoder read row decoder read column switch read column decoder memory a (128 64) matrix b (128 64) ad- dress deco- der read address control output latch timing control logic (2047) wdec rclk/clk rres/res wclk/wt wres/ds mode1 mode2 mode3 rdec (2047) dec1 (900,1810) dec2 (909,1819) dec3 (1134) dec4 (1125) ~ dout0 dout7 oe ~ ~ ~
4 HM63021 series HM63021 series absolute maximum ratings parameter symbol rating unit voltage on any pin relative to v ss v t ?.5 *1 to +7.0 v power dissipation p t 1.0 w operating temperature topr 0 to +70 ? storage temperature tstg ?5 to +125 ? storage temperature under bias tbias ?0 to +85 ? note: 1. ?.5 v for pulse width 10 ns. recommended dc operating conditions (ta = 0 to +70 ?) parameter symbol min typ max unit v cc 4.5 *1 5.0 5.5 v v ss 000v v ih 2.4 6.0 v v il ?.5 *2 0.8 v notes: 1. 4.75 for the HM63021fp28n and the HM63021p28n. 2. ?.0 v for pulse width 10 ns. dc and operating characteristics (ta = 0 to +70?, v cc = 5 v 10%, v ss = 0 v) parameter symbol min typ *1 max unit test condition input leakage current |i li | 10av cc = 5.5 v vin = v ss to v cc output leakage current |i lo | 10a oe = v ih vout = v ss to v cc operating power i cc 50 90 ma min. cycle, iout *2 = 0 ma supply current v ol 0.4 v i ol = 8 ma *3 dout 0 to dout 7, dec output pin 2.4 v i oh = ? ma, dout 0 to dout 7 pin 2.4 v i oh = ? ma, dec output pin notes: 1. typical values are at v cc = 5 v, ta = 25? and for reference only. 2. dout and dec 3. i ol = 6 ma for 45 ns version. capacitance (ta = 25 ?, ?= 1.0 mhz) parameter symbol min typ max unit conditions input capacitance cin 6 pf vin = 0 v output capacitance *2 cout 9 pf vout = 0 v notes: 1. these parameters are sampled and not 100% tested. 2. 13, 15?4, 26 pin v oh output voltage input voltage supply voltage
5 HM63021 series HM63021 series ac characteristics (v cc = 5 v 10% * , t a = 0 to +70?, unless otherwise noted) ac test conditions: input and output timing reference levels: 1.5 v input pulse levels: v ss to 3 v input rise and fall times: 5 ns note: 5 v for the HM63021fp28n and the HM63021p28n. HM63021-28/34 output load HM63021-45 output load dec output load note: 1. including scope and jig. +5 v 510 w 30 pf *1 395 w dec dout output load (a) +5 v 480 w 30 pf *1 255 w dout dout output load (b) (t olz, t ohz ) +5 v 480 w 5 pf *1 255 w dout dec output load note: 1. including scope and jig. +5 v 676 w 30 pf *1 495 w dec dout output load (a) +5 v 625 w 30 pf *1 294 w dout dout output load (b) (t olz, t ohz ) +5 v 625 w 5 pf *1 294 w dout +10% ?%
6 HM63021 series HM63021 series read cycle HM63021-28 HM63021-34 HM63021-45 parameter symbol min max min max min max unit read cycle time t rc 28 34 45 ns t rwl 10 10 15 ns t rwh 10 10 15 ns (fall) t ac 20 25 30 ns (rise) t da1 20 25 30 ns decode output access time t da2 40 50 60 ns output hold time t oh 5 5 5 ns (fall) t doh1 5 5 5 ns (rise) t doh2 5 5 5 ns output enable access time t oe 20 25 30 ns output disable to output in high z t ohz 0 15 0 20 0 25 ns output enable to output in low z t olz 5 5 5 ns input rise and fall time t t 3 50 3 50 3 50 ns write cycle HM63021-28 HM63021-34 HM63021-45 parameter symbol min max min max min max unit t wc 28 34 45 ns t wc (1h/2h mode) 56 68 90 ns t wwl 10 10 15 ns t wwh 10 10 15 ns input data setup time t ds 5 57ns input data hold time t dh 5 57ns t wesl 5 57ns t wesh 5 57ns t wehl 5 57ns t wehh 5 57ns t wtsl 5 57ns t wtsh 5 57ns t wthl 5 57ns t wthh 5 57ns input rise and fall time t t 3 50 3 50 3 50 ns wt hold time wt setup time we hold time we setup time write clock width write cycle time decode output hold time access time read clock width
7 HM63021 series HM63021 series mode description time base compression/expansion mode: turns the HM63021 into a 2048-word 8-bit fifo memory with asynchronous input/output. the HM63021 provides 2 clocks ( rclk , wclk ) and 2 resets for read and write ( rres , wres ). the internal address counters increment by 1 address clock and are reset to address 0. a write-inhibit function of the HM63021 stops writing automatically after the data has been written into all addresses 0 to 2047. the write-inhibit function is released by reset using wres , and the HM63021 restarts writing into address 0. double-speed conversion mode: turns the HM63021 into a 1024-word 8-bit 2 memory with asynchronous input/output. it is used for generating non-interlaced tv signals. when the original signal and the interpolated signal (1 field delay) of interlaced signals are input to the HM63021, multiplexed per dot, it outputs non- interlaced signals for each line. 8 fsc should be input to rclk and wclk . a standard h syn- chronizing signal and a non-interlace h syn- chronizing signal are input to wres and rres respectively. a write-inhibit function is provided in this mode, making it applicable to pal tv, where extra data (1135?024 = 111 bits) is ignored. tbc mode: turns the HM63021 into 2048-word 8-bit fifo memory with asynchronous input/ output. the HM63021 provides 2 clocks ( rclk , wclk ) and 2 resets ( rres , wres ), one each for read and write. the internal address counters increment by 1 address at each clock and are reset to address 0. the internal address counters return to address 0 after they reach address 2047. the HM63021 outputs a write decode pulse from wdec , synchronizing it with address 2047 in the write address counter, and read a decode pulse from rdec , synchronizing with address 2047 in the read address counter. using these pulses, the memory area can be extended easily (multiple- HM63021s can be used with ease). 1h/2h delay mode: turns the HM63021 into a 1024-word 8-bit 2 delay line with synchronous input/output. delay time is defined by the reset period of res . since the HM63021 outputs a 901 decode pulse ( dec1 ) and a 910 decode pulse ( dec2 ), connecting dec2 to res , for example, outputs 1h- and 2h- delayed signals alternately at an 8-fsc cycle when the original signal is input at a 4-fsc cycle. a write-inhibit function is provided in this mode, making it applicable to pal tv, where extra data (1135?024 = 111 bits) is ignored. delay line mode: turns the HM63021 into a 2048-word 8-bit delay line with synchronous input/output. delay time (3 to 2048 bits) is defined by the reset period of res . the delay is 2048 bits when res is fixed high. signals delayed by 910 bits to 1135 bits for example, can be easily obtained without external circuits by just connecting selected decoded pulses on dec1 dec4 to res . reset cycle HM63021-28 HM63021-34 HM63021-45 parameter symbol min max min max min max unit reset setup time t res 8910ns reset hold time t reh 557ns clock setup time before reset t reps 8910ns clock hold time before reset t reph 557ns input rise and fall time t t 350350350ns
8 HM63021 series HM63021 series read after write (3 bit delay) notes on using HM63021: hitachi recommends that pin 13 (high impedance) should be fixed by pulling up or down with a resistor (of several k ) in tbc or dsc mode. hitachi recommends that the mode signal input pins and ds pin should be fixed by pulling them up or down with a resistor (of several k ). data integrity cannot be guaranteed when mode or ds is changed during operation. when a read address coincides with a write address in tbce, tbc, or dsc mode, the data is written correctly but it is not always read correctly. at power on, the output of the address counter is not defined. therefore, operations before the system is reset cannot be guaranteed, and the decode signal output is not defined until after the first reset cycle. the decode signal is latched by a decode output latch circuit at the previous address of the internal counter address and is output- synchronized with the next address. for example, wdec in tbc mode is latched at write address 2046 and is output at write address 2047. if a write reset is performed on address 2047 at this time, the write address becomes 0 and wdec is output. the same operation is performed in other modes. when tbc or dsc or tbce mode is used, at least one rclk dummy cycle is required before starting write operation (before executing write pre-reset cycle) after power up. transition time of input level t t is defined as the rising time from v il to v ih and the falling time from v ih to v il . wclk rclk n n + 1 n + 2 t read cycle write cycle t 3 t wc min n ?1 n ?1 n n + 1 n ?2
9 HM63021 series HM63021 series in the reset cycle, the input levels of wres , rres , and res are raised to satisfy t reh , and are fixed high until t reph in the next pre-reset cycle is satisfied. the rise timings of the reset signals ( res , wres , rres ) are optional provided that the t reps specification is satisfied. the timings at which res , wres , and rres fall after pre-reset are also optional, provided that the t reph and t res specifications are satisfied. hitachi recommends that t m (time between mode set and the first cycle (pre-reset)) should be kept for 2 cycle times (56 ns/68 ns/90 ns) or more while the power supply is on. write after read (2048 bit delay) reset cycle wclk rclk t read cycle write cycle t 0 ns n n n + 1 n + 2 n + 1 n + 2 n + 3 n ?1 t reph t reh t res t reps t reph clk res wres rres
10 HM63021 series HM63021 series tbce, tbc, dsc, and delay line mode 1h/2h delay mode mode, ds valid mode set pre- reset reset t m clk wt res note: when mode pins are fixed with v cc and v ss is in mode set while the power supply is on, t m spec is not needed. mode wres (res) t m valid mode set pre- reset reset valid wclk (clk) note: when mode pins are fixed with v cc and v ss is in mode set while the power supply is on, t m spec is not needed.
11 HM63021 series HM63021 series internal output signal mode pin no. pin name address timing operation 13 wdec write 2047 after write 2047 completion of writing on all bits is detected. 26 rdec read 2047 output of 2046 completion of reading from all bits is detected. 13 dec1 read 900 (2h) output of 900 (1h) by inputting this signal to pin number 3, a 901/1802-bit delay output is obtained. 26 dec2 read 909 (2h) output of 909 (1r) by inputting this signal to pin number 3, a 910/1820-bit delay output is obtained. read 900 output of 899 by inputting this signal to pin number 3, a 901-bit delay output is obtained. read 1810 output of 1809 by inputting this signal to pin number 3 after the frequency of dec1 is divided into two, 1811-bit delay outputs are obtained. read 909 output of 908 by inputting this signal to pin number 3, a 910-bit delay output is obtained. read 1819 output of 1818 by inputting this signal to pin number 3 after the frequency of dec2 is divided into two, 1820-bit delay outputs are obtained. 16 dec3 read 1134 output of 1133 by inputting this signal to pin number 3, 1135-bit delay output is obtained. i 5 dec4 read 1125 output of 1124 by inputting this signal to pin number 3, 1126-bit delay output is obtained. note: when the counter is reset by a reset signal ( rres , res , wres ), the address becomes 0. dec2 26 dec1 13 delay line 1h/2h tbc decode signal when internal address counter reaches the specified address as shown below, decode outputs become low.
12 HM63021 series HM63021 series write-inhibit function mode write-inhibit function (internal counter address) tbce write-inhibit after address 2047 dsc write-inhibit after address 1023 2 tbc no function 1h/2h write-inhibit after address 1023 d no function note: when address counter is reset by wres or res , the address becomes 0. timing waveforms read reset cycle (tbce, tbc modes) when internal address counter is as follows, writing is inhibited automatically for the next cycle. the write-inhibit function is canceled by reset through wres or res . pre- reset reset address 0 output t rc t rc t rc t rwl t rwh t reph t res t reh t reps t oh t ac t oh t ac t oh t ac (n ?3) (n ?2) (n ?1) (n) (0) (1) rclk rres dout n ?1 cycle n cycle first cycle second cycle third cycle *2, *3 *1, *3 the read address counter is reset at the first falling edge of rclk after rres falls, meeting the specifications of t reps , and t reph , and it is not reset at the next falling edge of rclk even if rres is kept low. when t res , t reh , t reps , and t reph cannot meet the specifications, the reset operation is not guaranteed. in reset operation, both prereset and reset are required. output is from the read address of the previous cycle. when rres is fixed high, the data at the read address counter is reset after the data of address 2047 is output, and the same operation restarts. 1. 2. 3. notes:
13 HM63021 series HM63021 series write reset cycle (tbce, tbc modes) pre- reset reset address 0 t reps t reph t res t reh wclk wres *1 t ds t dh (n ?) (0) (1) (2) din we t wesl t wehl n ?1 cycle n cycle first cycle second cycle third cycle (n) the write address counter is reset at the first falling edge of wclk after wres falls, meeting the specifications of t reps and t reph , and it is not reset at the next falling edge of wclk even if wres is kept low. when t res , t reh , t reps , and t reph cannot meet the specifications, the reset operation is not guaranteed. in reset operation, both prereset and reset are required. note:
14 HM63021 series HM63021 series reset cycle (dsc modes) (b1) (b2) (b3) (a0) (a1) (a2) (a3) (b0) (b1) (b2) (b3) t res t reh t reph t reh t res t reps t res t reh t reph t dh t ds pre-reset pre-reset pre-reset reset pre-reset t reh t res t reph t reps t ac t reps t oh t reph t ac t oh (a3) (b3) (a0) (b1) (a1) (a2) (b3) (a3) (a0) wclk wres din rclk rres dout reset timing 1 reset timing 2 (b0) (b2) reset (b0) *1, *3, *4 *2, *3, *4 t reh t res reset the write address counter is reset at the first falling edge of wclk after wres falls, meeting the specifications of t reps and t reph , and is not reset at the next falling edge of wclk even if wres is kept low. when t res , t reh , and t reph cannot meet the specifications, the reset operation is not guaranteed. the read address counter is reset at the first falling edge of rclk after rres falls, meeting the specifications of t reps and t reph , and it is not reset at the next falling edge of rclk even if rres is kept low. when t res , t reh , t reps , and t reph cannot meet the specifications, reset operation is not guaranteed. when t reph , t res , t reh ( wres to wclk ), t res , t reh , ( wres to rclk ) or t reps , t reph , t res , t reh ( rres to rclk ) cannot meet the specifications, the output of video signal a is not guaranteed (reset timing 1). when t reps ( wres to rclk ), or t res , t reh , t reps , t reph ( rres to rclk ) cannot meet the specifications, the interpolation signal b is not guaranteed (reset timing 2). notes: 1. 2. 3. 4.
15 HM63021 series HM63021 series reset cycle (1h/2h modes) t wc reset pre- reset t rc t rc t wtsl t wthl t wtsh t wthh t reph t reps t res t reh n ?2 0 t ds t dh *1 n ?2 n ?1 n n 0 0 1 t ac t oh t oh t oh t ac t ac 2h 1h 1h 2h 1h 2h 1h t wehl t wesl high or low clk (8 f sc ) wt (4 f sc ) res din dout we ds address 0 input address 0 (2h) output address 0 (1h) output *3 *3 *1, *3 *2 *1 n ?1 n n ?1 2h wt is the input during half cycle of clk , meeting the specifications of t wtsl , t wthl , t wtsh , and t wthh . data is written when wt is low. reset is possible when wt is high. read address counter is reset at the first falling edge of clk after res falls, meeting the specifications of t reps and t reph , and it is not reset at the next falling edge of clk even if res is kept low. when t res , t reh , t reps , and t reph cannot meet the specifi- cations, the reset operation is not guaranteed. in reset operation, both prereset and reset are required. when ds is fixed high, 1h output date is delayed by n bits and 2h output data is delayed by 2n bits where 2n is the reset cycle of res . when ds is fixed low, 1h output data is delayed by n-5 bits and 2h output data is delayed by 2n-5 bits. notes: 1. 2. 3.
16 HM63021 series HM63021 series reset cycle (d modes) write enable (tbce, dsc, tbc, d modes) reset pre-reset t reph t reps t res t reh t wehl t wesl (n ?3) (n ?2) (1) (2) (n ?3) (n ?2) (n ?1) (n) (0) (1) (2) t dh t ds t ac t oh t ac clk res we din dout (n ?1) (n) (0) *1 t oh the read address counter is reset at the first falling edge of clk after res falls, meeting the specifications of t reps and t reph , and it is not reset at the next falling edge of clk even if res is kept low. when t res , t reh , t reps , and t reph cannot meet the specifications, the reset operation is not guaranteed. in reset operation, both prereset and reset are required. note: t wwl t wwh t wc t wehl t wesh t wehh t wesl t dh t ds n n +1 n+4 n+5 we din wclk n cycle n + 1 cycle n + 2 cycle n + 3 cycle n + 4 cycle *1 *2 (clk) *1 *1 when t wehl , t wesh , t wehh , and t wesl cannot meet this specifications, the write enable operation is not guaranteed. in the delay line mode, clk takes the place of wclk . notes: 1. 2.
17 HM63021 series HM63021 series write enable (1h/2h mode) decode output (tbc, d modes) decode output (1h/2h modes) t wc t wwh t wwh t wthl t wtsl t wtsl t wthl t wtsh t wthh t wehl t wesl t wesh t wehh t wesl t dh t ds (n) (n+1) (n+3) clk (8 f sc ) wt (4 f sc ) we din *1 t wwl t wwl when t wtsl , t wthl , t wehz , and t wehh cannot meet the specifications, the write enable operation is not guaranteed. note: t da1 t doh1 t da2 t doh2 dec *2 clk *1 wclk rclk in tbc mode, wclk or rclk takes the palce of clk . dec is wdec or rdec in tbc , dec1 , dec2 , dec2 , or dec4 in d mode. notes: 1. 2. t wthl t wtsl clk wt *1 dec1 t wtsh t wthh t wtsh t wthh t da1 t doh1 t da2 t doh2 t wtsl t wthl dec2 when t wtsl , t wthl , t wtsh , and t wthh cannot meet the specifications, the decode output operation is not guaranteed. note:
18 HM63021 series HM63021 series output enable (all modes) t oe t olz t ohz data valid data valid high z oe dout *1 transition of t ohz and t wlz is measured ?00 mv from steady state voltage with output load b. these parameters are sampled and not 100% tested. note:

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